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PRODUCT SPECIFICATION
Military Operating Temperature Range Military Operating Temperature Range
PE83501
Product Description
The PE83501 is a high-performance dynamic CMOS prescaler with a fixed divide ratio of 2. Its operating frequency range is 400 MHz to 3.5 GHz. The PE83501 operates on a nominal 3 V supply and draws only 12 mA. It is packaged in a small 8-lead MSOP and is ideal for frequency scaling and microwave PLL synthesis solutions. The PE83501 is manufactured in Peregrine's patented Ultra-Thin Silicon (UTSi ) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS.
3.5 GHz Low Power CMOS Divide-by-2 Prescaler
Features * High-frequency operation: 400 MHz to 3.5 GHz * Fixed divide ratio of 2 * Low-power operation: 12 mA typical @ 3 V * Small package: 8-lead MSOP * Low cost
Figure 1. Functional Schematic Diagram
Figure 2. Package Drawing
3.05 2.85
Fin
PREAMP
D CLK DEC
Q QB
DRIVER OUTPUT BUFFER
Fout
8-lead MSOP
OFF-CHIP BYPASS
5.05 4.75
Table 1. Electrical Specifications (ZS = ZL = 50 )
2.85V VDD 3.15 V; -55 C TA 125 C, unless otherwise specified
Parameter
Supply Voltage Supply Current Input Frequency (Fin) Input Power (Pin)
Conditions
Minimum
2.85
Typical
3.0 13
Maximum
3.15 18 3500 +10 +10 +10
Units
V mA MHz dBm dBm dBm dBm
400 400 MHz Fin 2.0 GHz 2.0 GHz < Fin 2.8 GHz 2.8 GHz < Fin 3.5 GHz -10 0 +5 -15
Output Power (Pout)
400 MHz Fin 3.5 GHz
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Copyright Peregrine Semiconductor Corp. 2003
Page 1 of 7
PE83501
Product Specification
Figure 3. Pin Configuration
VDD Fin DEC GND 1 2 8 7 GND Fout GND GND
Electrostatic Discharge (ESD) Precautions When handling this UTSi device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 3. Latch-Up Avoidance Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up.
PE83501
3 4 6 5
Table 2. Pin Descriptions
Pin No.
1 2 3
Pin Name
VDD Fin DEC
Description
Power supply pin. Bypassing is required. Input signal pin. DC blocking capacitor required (15 pF typical) Power supply decoupling pin. Place a capacitor as close as possible and connect directly to the ground plane. Ground pin. Ground pattern on the board should be as wide as possible to reduce ground impedance. Ground pin. Ground pin. Divided frequency output pin. DC blocking capacitor required (47 pF typical) Ground pin.
Device Functional Considerations The PE83501 divides a 400 MHz to 3.5 GHz input signal by two, producing a 200 MHz to 1.75 GHz output signal. To work properly, pin 3 must be supplied with a bypass capacitor to ground. In addition, the input and output signals (pins 2 & 7) must be AC coupled via an external capacitor, as shown in the test circuit in Figure 4. The ground pattern on the board should be made as wide as possible to minimize ground impedance. See Figure 11 for a layout example.
4
GND
5 6 7 8
GND GND Fout GND
Table 3. Absolute Maximum Ratings
Symbol
VDD Pin TST TOP VESD
Parameter/Conditions
Supply voltage Input Power Storage temperature range Operating temperature range ESD voltage (Human Body Model)
Min
Max
4.0 15
Units
V dBm C C V
-65 -55 250
150 125
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0124~00B
| UTSi CMOS RFIC SOLUTIONS
Page 2 of 7
PE83501
Product Specification
Figure 4. Test Circuit Block Diagram
VDD 3 V +/ 0.15 V -
10 pF 1000 pF 1 8 50 2 15 pF 3 7
50
PE83501
8 Lead MSOP 6 5 N/C 4
47 pF
Spectrum Analyzer
Signal Generator
10 nF
10 pF
Figure 5. High Frequency System Application The wideband frequency of operation of the PE83501 makes it an ideal part for use in a DBS downconverter system.
INPUT FROM DBS 1ST IF BASEBAND OUTPUT
BPF
SAW
AGC
FM DEMOD
DIVIDE-BY-2
PE3236 PE83501
LOW NOISE PLL SYNTH
LPF
PEREGRINE SEMICONDUCTOR CORP. |
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Copyright Peregrine Semiconductor Corp. 2003
Page 3 of 7
PE83501
Product Specification
Typical Performance Data: VDD = 3.0V
Figure 6. Input Sensitivity
Figure 7. Device Current
Figure 8. Output Power
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0124~00B
| UTSi CMOS RFIC SOLUTIONS
Page 4 of 7
PE83501
Product Specification
Figure 10. Evaluation Board Schematic Diagram
J2-7
Figure 11. Evaluation Board Layout
10 pF
1000 pF VDD GND
IN J1 C1 C3 DEC 10 nF 10 pF GND
OUT C2 C1 NC J3
GND
J4
J5
Evaluation Kit Operation The MSOP Prescaler Evaluation Board was designed to help customers evaluate the PE83501 Divide-by-2 Prescaler. On this board, the device input (pin 2) is connected to connector J1 through a 50 transmission line. A series capacitor (C3) provides the necessary DC block for the device input. It is important to note that the value of this capacitance will impact the performance of the device. A value of 15 pF was found to be optimal for this board layout; other applications may require a different value. The device output (pin 7) is connected to connector J3 through a 50 transmission line. A series capacitor (C1) provides the necessary DC block for the device output. Note that this capacitor must be chosen to have a low impedance at the desired output frequency the device. The value of 47 pF was chosen to provide a wide operating range for the evaluation board. The board is constructed of a two-layer FR4 material with a total thickness of 0.031". The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide above ground plane model with trace width of 0.030", trace gaps of 0.007", dielectric thickness of 0.028", metal thickness of 0.0014" and r of 4.4. Note that the predominate mode for these transmission lines is coplanar waveguide. J2 provides DC power to the device. Starting from the lower left pin, the second pin to the right (J2-3) is connected to the device VDD pin (1). Two decoupling capacitors (10 pF, 1000 pF) are included on this trace. It is the responsibility of the customer to determine proper supply decoupling for their design application. The DEC pin (3) must be connected to a low impedance AC ground for proper device operation. On the board, two decoupling capacitors (C6 = 10 nF, C4 = 10 pF), located on the back of the board, perform this function. Applications Support If you have a problem with your evaluation kit or if you have applications questions call (858) 455-0660 and ask for applications support. You may also contact us by fax or e-mail: Fax: (858) 455-0770 E-Mail: help@peregrine-semi.com
PEREGRINE SEMICONDUCTOR CORP. |
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Copyright Peregrine Semiconductor Corp. 2003
Page 5 of 7
PE83501
Product Specification
Figure 10. Package Drawing
8-Lead MSOP
TOP VIEW 0.65BSC 8 7 6 5 .525BSC
2.450.10 2X 3.000.10
0.510.13 -B1 2 3 4 .25 A B C
0.510.13
2.950.10
-C0.860.08 2.950.10
1.10 MAX -A0.10 A 0.33+0.07 -0.08 0.08 ABC 3.000.10 FRONT VIEW SIDE VIEW 0.100.05 3.000.10 4.900.15
Table 6. Ordering Information
Order Code
83501-11 83501-12 83501-00
Part Marking
PE83501 PE83501 PE83501-EK
Description
PE83501-08MSOP-100A PE83501-08MSOP-2000C PE83501-08MSOP-EK
Package
8-lead MSOP 8-lead MSOP Evaluation Board
Shipping Method
50 pcs. / Tube 2000 pcs. / T&R 1 / Box
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0124~00B
| UTSi CMOS RFIC SOLUTIONS
Page 6 of 7
PE83501
Product Specification
Sales Offices
United States
Peregrine Semiconductor Corp.
6175 Nancy Ridge Drive San Diego, CA 92121 Tel 1-858-455-0660 Fax 1-858-455-0770
Japan
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower 1-1-1 Uchisiawaicho, Chiyoda-ku, Tokyo, Japan 100-011 Tel. 011-81-3-3502-5211 Fax. 011-81-3-3502-5213
Europe
Peregrine Semiconductor Europe
Aix-En-Provence Office Parc Club du Golf, bat 9 13856 Aix-En-Provence Cedex 3 France Tel 33-0-4-4239-3360 Fax 33-0-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: http://www.peregrine-semi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice.
The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Peregrine products are protected under one or more of the following U.S. patents: 6,090,648; 6,057,555; 5,973,382; 5,973,363; 5,930,638; 5,920,233; 5,895,957; 5,883,396; 5,864,162; 5,863,823; 5,861,336; 5,663,570; 5,610,790; 5,600,169; 5,596,205; 5,572,040; 5,492,857; 5,416,043. Other patents are pending.
Preliminary Specification
The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a PCN (Product Change Notice).
Peregrine, the Peregrine logotype, Peregrine Semiconductor Corp., and UTSi are registered trademarks of Peregrine Semiconductor Corporation. Copyright (c) 2003 Peregrine Semiconductor Corp. All rights reserved.
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Copyright Peregrine Semiconductor Corp. 2003
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